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CY7C245A - 2K x 8 Reprogrammable Registered PROM

Download the CY7C245A datasheet PDF. This datasheet also covers the CY7 variant, as both devices belong to the same 2k x 8 reprogrammable registered prom family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C245A is a high-performance, 2K x 8, electrically programmable, read-only memory packaged in a slim 300-mil plastic or hermetic DIP.

The ceramic package may be equipped with an erasure window; when exposed to UV light the PROM is erased and can then be reprogrammed.

Features

  • Windowed for reprogrammability.
  • CMOS for optimum speed/power.
  • High speed.
  • 15-ns address set-up.
  • 10-ns clock to output.
  • Low power.
  • 330 mW (commercial) for -25 ns.
  • 660 mW (military).
  • Programmable synchronous or asynchronous output enable.
  • On-chip edge-triggered registers.
  • Programmable asynchronous register (INIT).
  • EPROM technology, 100% programmable.
  • Slim, 300-mil, 24-pin plastic o.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7-C245.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY7C245A 2K x 8 Reprogrammable Registered PROM Features • Windowed for reprogrammability • CMOS for optimum speed/power • High speed — 15-ns address set-up — 10-ns clock to output • Low power — 330 mW (commercial) for -25 ns — 660 mW (military) • Programmable synchronous or asynchronous output enable • On-chip edge-triggered registers • Programmable asynchronous register (INIT) • EPROM technology, 100% programmable • Slim, 300-mil, 24-pin plastic or hermetic DIP • 5V ±10% VCC, commercial and military • TTL-compatible I/O • Direct replacement for bipolar PROMs • Capable of withstanding greater than 2001V static discharge Logic Block Diagram INIT A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CP COLUMN ADDRESS ADDRESS DECODER PROGRAMMABLE INITIALIZE WORD ROW ADDRESS PROGRAMMABLE ARRAY MULTIPLEXER O 7 F
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