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CY7C1513KV18 - (CY7C15xxKV18) 72-Mbit QDR II SRAM 4-Word Burst Architecture

Download the CY7C1513KV18 datasheet PDF. This datasheet also covers the CY7C1511KV18 variant, as both devices belong to the same (cy7c15xxkv18) 72-mbit qdr ii sram 4-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1526KV18, CY7C1513KV18, and CY7C1515KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II architecture.

QDR II architecture consists of two separate ports: the read port and the write port to access the memory array.

Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 333 MHz clock for high bandwidth.
  • Four-word burst for reducing address bus frequency.
  • Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
  • Echo cl.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1511KV18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1513AV18 72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1513JV18 72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1513V18 (CY7C15xxV18) SRAM 4-Word Burst Architecture
CY7C1510AV18 72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1510V18 1.8V Synchronous Pipelined SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 72-Mbit QDR® II SRAM Four-Word Burst Architecture 72-Mbit QDR® II SRAM Four-Word Burst Architecture Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 333 MHz clock for high bandwidth ■ Four-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high speed systems ■ Single multiplexed address input bus latches address inputs for read and write ports ■ Separate port selects for depth expan
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