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CY7C1487V25 - 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM

Description

The CY7C1481V25/CY7C1483V25/CY7C1487V25 is a 2.5V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high-speed microprocessors with minimum glue logic.

Maximum access delay from clock rise is 6.5 ns (133-MHz version).

Features

  • Supports 133 MHz bus operations 2M x 36/4M x 18/1M x 72 common IO 2.5V core power supply (VDD) 2.5V or 1.8V IO supply (VDDQ) Fast clock-to-output time Functional.

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CY7C1481V25 CY7C1483V25 CY7C1487V25 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM Features • • • • • Supports 133 MHz bus operations 2M x 36/4M x 18/1M x 72 common IO 2.5V core power supply (VDD) 2.5V or 1.8V IO supply (VDDQ) Fast clock-to-output time Functional Description[1] The CY7C1481V25/CY7C1483V25/CY7C1487V25 is a 2.5V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK).
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