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CY7C1465AV25 - Flow-Through SRAM

Download the CY7C1465AV25 datasheet PDF. This datasheet also covers the CY7C1461AV25 variant, as both devices belong to the same flow-through sram family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1461AV25/CY7C1463AV25/CY7C1465AV25 are 2.5V, 1M × 36/2M × 18/512K × 72 Synchronous Flow-through Burst SRAMs designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

Features

  • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.
  • Can support up to 133-MHz bus operations with zero wait states.
  • Data is transferred on every clock.
  • Pin-compatible and functionally equivalent to ZBT™ devices.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Registered inputs for flow-through operation.
  • Byte Write capability.
  • 2.5V/1.8V I/O power supply.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1461AV25_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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CY7C1006D 1-Mbit (256K x 4) Static RAM Cypress
CY7C1011G 2-Mbit (128K words x 16 bit) Static RAM Cypress
CY7C1041G 4-Mbit (256K words x 16 bit) Static RAM Cypress

Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1465AV33 Flow-Through SRAM
CY7C146 2K x 8 Dual-Port Static RAM
CY7C1460AV25 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM
CY7C1460AV33 36-Mbit Pipelined SRAM
CY7C1460BV25 36-Mbit (1 M x 36/2 M x 18) Pipelined SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY7C1461AV25 CY7C1463AV25 www.DataSheet4U.com CY7C1465AV25 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM with NoBL™ Architecture Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin-compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 2.5V/1.8V I/O power supply • Fast clock-to-output times — 6.
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