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CY7C1463BV33
36-Mbit (2 M × 18) Flow-Through SRAM with NoBL™ Architecture
36-Mbit (2 M × 18) Flow-Through SRAM with NoBL™ Architecture
Features
■ No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
■ Supports up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock
■ Pin-compatible and functionally equivalent to ZBT™ devices ■ Internally self timed output buffer control to eliminate the need
to use OE ■ Registered inputs for flow through operation ■ Byte Write capability ■ 3.3 V/2.5 V I/O power supply ■ Fast clock-to-output times
❐ 6.
CY7C1463BV33 Datasheet
