Datasheet4U Logo Datasheet4U.com

CY7C1427AV18 - (CY7C14xxAV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture

Download the CY7C1427AV18 datasheet PDF. This datasheet also covers the CY7C1416AV18 variant, as both devices belong to the same (cy7c14xxav18) 36-mbit ddr-ii sram 2-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1416AV18, CY7C1427AV18, CY7C1418AV18, and CY7C1420AV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture.

The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter.

Features

  • 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36).
  • 250-MHz clock for high bandwidth.
  • 2-Word burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces (data transferred at 500 MHz) @ 250 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two output clocks (C and C) account for clock skew and flight time mismatching.
  • Echo clocks (CQ and CQ) simplify data capture in high-spe.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1416AV18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C1460SV25 36-Mbit (1M x 36/2M x 18) Pipelined SRAM Cypress
CY7C1462SV25 36-Mbit (1M x 36/2M x 18) Pipelined SRAM Cypress
CY7C1006D 1-Mbit (256K x 4) Static RAM Cypress
CY7C1011G 2-Mbit (128K words x 16 bit) Static RAM Cypress
CY7C1041G 4-Mbit (256K words x 16 bit) Static RAM Cypress

Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1427BV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1427JV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C142 2K x 8 Dual-Port Static RAM
CY7C1420AV18 (CY7C14xxAV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1420BV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com PRELIMINARY CY7C1416AV18 CY7C1427AV18 CY7C1418AV18 CY7C1420AV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture Features • 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 500 MHz) @ 250 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two output clocks (C and C) account for clock skew and flight time mismatching • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Synchronous internally self-timed writes • 1.8V core power supply with HSTL inputs and outputs • Variable drive HSTL output buffers • Expanded HSTL output voltage (1.4V–VDD) • 15 x 17 x 1.4 mm 1.
Published: |