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CY7C1425V18 - (CY7C14xxV18) SRAM 2-Word Burst Architecture

Download the CY7C1425V18 datasheet PDF. This datasheet also covers the CY7C1412V18 variant, as both devices belong to the same (cy7c14xxv18) sram 2-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1410V18, CY7C1425V18, CY7C1412V18, and CY7C1414V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture.

QDR-II architecture consists of two separate ports to access the memory array.

Features

  • Separate Independent Read and Write data ports.
  • Supports concurrent transactions.
  • 200-MHz clock for high bandwidth.
  • 2-Word Burst on all accesses.
  • Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 400 MHz) @ 200 MHz www. DataSheet4U. com.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two output clocks (C and C) accounts for clock skew and flight time mismatchi.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1412V18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1425AV18 36-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1425JV18 (CY7C14xxJV18) SRAM 2-Word Burst Architecture
CY7C1425KV18 36-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C142 2K x 8 Dual-Port Static RAM
CY7C1420AV18 (CY7C14xxAV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture

Full PDF Text Transcription

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PRELIMINARY CY7C1410V18 CY7C1425V18 CY7C1412V18 CY7C1414V18 36-Mbit QDR-II™ SRAM 2-Word Burst Architecture Features • Separate Independent Read and Write data ports — Supports concurrent transactions • 200-MHz clock for high bandwidth • 2-Word Burst on all accesses • Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 400 MHz) @ 200 MHz www.DataSheet4U.
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