Datasheet4U Logo Datasheet4U.com

CY7C1417AV18 - 1.8V Synchronous Pipelined SRAM

Features

  • 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36).
  • 300-MHz clock for high bandwidth.
  • 4-Word burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches.
  • Echo clocks (CQ and CQ) simplify data captu.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C1460SV25 36-Mbit (1M x 36/2M x 18) Pipelined SRAM Cypress
CY7C1462SV25 36-Mbit (1M x 36/2M x 18) Pipelined SRAM Cypress
CY7C1006D 1-Mbit (256K x 4) Static RAM Cypress
CY7C1011G 2-Mbit (128K words x 16 bit) Static RAM Cypress
CY7C1041G 4-Mbit (256K words x 16 bit) Static RAM Cypress

Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C141 1K x 8 Dual-Port Static RAM
CY7C1410AV18 (CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1410JV18 (CY7C14xxJV18) SRAM 2-Word Burst Architecture
CY7C1410V18 (CY7C14xxV18) SRAM 2-Word Burst Architecture
CY7C1411AV18 (CY7C14xxAV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture

Full PDF Text Transcription

Click to expand full text
CY7C1417AV18 CY7C1428AV18 CY7C1419AV18 CY7C1421AV18 36-Mbit DDR-II SRAM 4-Word Burst Architecture Features • 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) • 300-MHz clock for high bandwidth • 4-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Synchronous internally self-timed writes • 1.8V core power supply with HSTL inputs and outputs • Variable drive HSTL output buffers • Expanded HSTL output voltage (1.4V–VDD) • Available in 165-ball FBGA package (15 x 17 x 1.
Published: |