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CY7C1416BV18 - 36-Mbit DDR-II SRAM 2-Word Burst Architecture

Download the CY7C1416BV18 datasheet PDF. This datasheet also covers the CY7C1418BV18 variant, as both devices belong to the same 36-mbit ddr-ii sram 2-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1416BV18, CY7C1427BV18, CY7C1418BV18, and CY7C1420BV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture.

The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter.

Features

  • Functional.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1418BV18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (Infineon)

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Full PDF Text Transcription

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www.DataSheet4U.com CY7C1416BV18, CY7C1427BV18 CY7C1418BV18, CY7C1420BV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture Features ■ ■ ■ ■ ■ Functional Description The CY7C1416BV18, CY7C1427BV18, CY7C1418BV18, and CY7C1420BV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided.
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