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CY7C1414JV18 - (CY7C14xxJV18) SRAM 2-Word Burst Architecture

Download the CY7C1414JV18 datasheet PDF. This datasheet also covers the CY7C1412JV18 variant, as both devices belong to the same (cy7c14xxjv18) sram 2-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1410JV18, CY7C1425JV18, CY7C1412JV18, and CY7C1414JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture.

QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array.

Features

  • Configurations CY7C1410JV18.
  • 4M x 8 CY7C1425JV18.
  • 4M x 9 CY7C1412JV18.
  • 2M x 18 CY7C1414JV18.
  • 1M x 36 Separate independent read and write data ports.
  • Supports concurrent transactions 267 MHz clock for high bandwidth 2-word burst on all accesses (data transferred at 534 MHz) at 267 MHz.
  • Double Data Rate (DDR) interfaces on both read and write ports www. DataSheet4U. com.
  • Functional.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1412JV18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1414AV18 (CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture
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Full PDF Text Transcription

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CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 36-Mbit QDR™-II SRAM 2-Word Burst Architecture Features ■ Configurations CY7C1410JV18 – 4M x 8 CY7C1425JV18 – 4M x 9 CY7C1412JV18 – 2M x 18 CY7C1414JV18 – 1M x 36 Separate independent read and write data ports ❐ Supports concurrent transactions 267 MHz clock for high bandwidth 2-word burst on all accesses (data transferred at 534 MHz) at 267 MHz ■ ■ ■ Double Data Rate (DDR) interfaces on both read and write ports www.DataSheet4U.com ■ Functional Description The CY7C1410JV18, CY7C1425JV18, CY7C1412JV18, and CY7C1414JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array.
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