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CY7C12431KV18 - 36-Mbit QDR II SRAM 4-Word Burst Architecture

Download the CY7C12431KV18 datasheet PDF. This datasheet also covers the CY7C12411KV18 variant, as both devices belong to the same 36-mbit qdr ii sram 4-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C12411KV18, CY7C12561KV18, CY7C12431KV18, and CY7C12451KV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture.

Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array.

Features

  • Functional.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C12411KV18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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CY7C1041G 4-Mbit (256K words x 16 bit) Static RAM Cypress
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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1243KV18 36-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1243V18 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C12411KV18 36-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1241KV18 36-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1241V18 36-Mbit QDR-II SRAM 4-Word Burst Architecture

Full PDF Text Transcription

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36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) CY7C12411KV18, CY7C12561KV18 CY7C12431KV18, CY7C12451KV18 ® Features ■ Functional Description The CY7C12411KV18, CY7C12561KV18, CY7C12431KV18, and CY7C12451KV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.
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