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CY7C1150V18 - (CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture

Download the CY7C1150V18 datasheet PDF. This datasheet also covers the CY7C1146V18 variant, as both devices belong to the same (cy7c11xxv18) 18-mbit ddr-ii sram 2-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1146V18, CY7C1157V18, CY7C1148V18, and CY7C1150V18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II+ architecture.

The DDR-II+ consists of an SRAM core with advanced synchronous peripheral circuitry.

Features

  • Functional.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1146V18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1150KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C1156V18 (CY7C11xxV18) SRAM 4-Word Burst Architecture
CY7C1157V18 (CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1141V18 (CY7C11xxV18) SRAM 4-Word Burst Architecture
CY7C1143KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture

Full PDF Text Transcription

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CY7C1146V18 CY7C1157V18 CY7C1148V18 CY7C1150V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features ■ ■ ■ ■ ■ ■ Functional Description The CY7C1146V18, CY7C1157V18, CY7C1148V18, and CY7C1150V18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II+ architecture. The DDR-II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 8-bit words (CY7C1146V18) or 9-bit words (CY7C1157V18) or 18-bit words (CY7C1148V18) or 36-bit words (CY7C1150V18) that burst sequentially into or out of the device.
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