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CY7C1145V18 - (CY7C11xxV18) SRAM 4-Word Burst Architecture

Download the CY7C1145V18 datasheet PDF. This datasheet also covers the CY7C1141V18 variant, as both devices belong to the same (cy7c11xxv18) sram 4-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1141V18, CY7C1156V18, CY7C1143V18, and CY7C1145V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture.

QDR-II+ architecture consists of two separate ports to access the memory array.

Features

  • Separate Independent read and write data ports.
  • Supports concurrent transactions.
  • 300 MHz to 375 MHz clock for high bandwidth.
  • 4-Word Burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 750 MHz) at 375 MHz.
  • Read latency of 2.0 clock cycles.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ) simplify data capture in high speed syste.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1141V18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1145KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C1141V18 (CY7C11xxV18) SRAM 4-Word Burst Architecture
CY7C1143KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C1143V18 (CY7C11xxV18) SRAM 4-Word Burst Architecture
CY7C1146V18 (CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture

Full PDF Text Transcription

Click to expand full text
CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 18-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Features Separate Independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz to 375 MHz clock for high bandwidth ■ 4-Word Burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 750 MHz) at 375 MHz ■ Read latency of 2.
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