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CY7C109 - Straight 1-Row BergStik II Headers

Download the CY7C109 datasheet PDF. This datasheet also covers the CY7C1009 variant, as both devices belong to the same straight 1-row bergstik ii headers family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C109 / CY7C1009 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits.

Features

  • High speed.
  • tAA = 10 ns.
  • Low active power.
  • 1017 mW (max. , 12 ns).
  • Low CMOS standby power.
  • 55 mW (max. ), 4 mW (Low power version).
  • 2.0V Data Retention (Low power version).
  • Automatic power-down when deselected.
  • TTL-compatible inputs and outputs.
  • Easy memory expansion with CE1, CE2, and OE options active HIGH chip enable (CE2), an active LOW output enable (OE), and three-state drivers. Writing to the device i.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1009_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C1006D 1-Mbit (256K x 4) Static RAM Cypress
CY7C1011G 2-Mbit (128K words x 16 bit) Static RAM Cypress
CY7C1041G 4-Mbit (256K words x 16 bit) Static RAM Cypress
CY7C1041GE 4-Mbit (256K words x 16 bit) Static RAM Cypress
CY7C1041GN 4-Mbit (256K words x 16 bit) Static RAM Cypress

Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C109B 128K x 8 Static RAM
CY7C109D 1-Mbit (128 K x 8) Static RAM
CY7C109V33 Straight 1-Row BergStik II Headers
CY7C1006B 256K x 4 Static RAM
CY7C1007 (CY7C107 / CY7C1007) 1M x 1 Static RAM

Full PDF Text Transcription

Click to expand full text
009 CY7C109 CY7C1009 128K x 8 Static RAM Features • High speed — tAA = 10 ns • Low active power — 1017 mW (max., 12 ns) • Low CMOS standby power — 55 mW (max.), 4 mW (Low power version) • 2.0V Data Retention (Low power version) • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE1, CE2, and OE options active HIGH chip enable (CE2), an active LOW output enable (OE), and three-state drivers. Writing to the device is accomplished by taking chip enable one (CE1) and write enable (WE) inputs LOW and chip enable two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16).
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