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CY7C1020 - 32K x 16 Static RAM

Download the CY7C1020 datasheet PDF. This datasheet also covers the CY7 variant, as both devices belong to the same 32k x 16 static ram family and are provided as variant models within a single manufacturer datasheet.

Description

of read and write modes.

The input/output pins (I/O 1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW).

Features

  • 5.0V operation (± 10%).
  • High speed.
  • tAA = 10 ns.
  • Low active power.
  • 825 mW (max. , 10 ns, “L” version).
  • Very Low standby power.
  • 550 µW (max. , “L” version).
  • Automatic power-down when deselected.
  • Independent Control of Upper and Lower bytes.
  • Available in 44-pin TSOP II and 400-mil SOJ (BLE) is LOW, then data from I/O pins (I/O 1 through I/O8), is written into the location specified on the address pins (A0 thro.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7-C102.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C1006D 1-Mbit (256K x 4) Static RAM Cypress
CY7C1011G 2-Mbit (128K words x 16 bit) Static RAM Cypress
CY7C1041G 4-Mbit (256K words x 16 bit) Static RAM Cypress
CY7C1041GE 4-Mbit (256K words x 16 bit) Static RAM Cypress
CY7C1041GN 4-Mbit (256K words x 16 bit) Static RAM Cypress

Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1020CV26 512-Kbit (32 K x 16) Static RAM
CY7C1020CV33 512 K (32 K x 16) Static RAM
CY7C1020D 512-Kbit (32 K x 16) Static RAM
CY7C1020DV33 512 K (32 K x 16) Static RAM
CY7C1020V 32K x 16 Static RAM

Full PDF Text Transcription

Click to expand full text
7C10 CY7C1020 32K x 16 Static RAM Features • 5.0V operation (± 10%) • High speed — tAA = 10 ns • Low active power — 825 mW (max., 10 ns, “L” version) • Very Low standby power — 550 µW (max., “L” version) • Automatic power-down when deselected • Independent Control of Upper and Lower bytes • Available in 44-pin TSOP II and 400-mil SOJ (BLE) is LOW, then data from I/O pins (I/O 1 through I/O8), is written into the location specified on the address pins (A0 through A14). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O 9 through I/O16) is written into the location specified on the address pins (A0 through A14). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
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