Download the AZ10EL32 datasheet PDF. This datasheet also covers the AZ100EL32 variant, as both devices belong to the same ecl/pecl / 2 divider family and are provided as variant models within a single manufacturer datasheet.
The AZ10/100EL32 is an integrated ÷2 divider.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple EL32’s in a system.
| Part number | AZ10EL32 |
|---|---|
| Manufacturer | Arizona |
| File Size | 130.18 KB |
| Description | ECL/PECL / 2 Divider |
| Datasheet |
 AZ10EL32 Datasheet
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| Part Number | Description |
|---|---|
| AZ10EL31 | ECL/PECL D Flip-Flop |
| AZ10EL07 | ECL/PECL 2-Input XOR/XNOR |
| AZ10EL11 | ECL/PECL 1:2 Differential Fanout Buffer |
| AZ10ELT20 | CMOS/TTL to Differential PECL Translator |
| AZ10E111 | 1:9 Differential Clock Driver |
| AZ100E111 | 1:9 Differential Clock Driver |
| AZ100EL07 | ECL/PECL 2-Input XOR/XNOR |
| AZ100EL11 | ECL/PECL 1:2 Differential Fanout Buffer |
| AZ100EL16VS | ECL/PECL Differential Receiver |
| AZ100EL31 | ECL/PECL D Flip-Flop |
The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.
