Datasheet Details
| Part number | AZ100LVEL32 |
|---|---|
| Manufacturer | Arizona Microtek |
| File Size | 203.99 KB |
| Description | ECL/PECL / 2 Divider |
| Datasheet |
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The AZ10/100LVEL32 is an integrated ÷2 divider.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple LVEL32’s in a system.
| Part number | AZ100LVEL32 |
|---|---|
| Manufacturer | Arizona Microtek |
| File Size | 203.99 KB |
| Description | ECL/PECL / 2 Divider |
| Datasheet |
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| Part Number | Description |
|---|---|
| AZ100LVEL33 | ECL/PECL / 4 Divider |
| AZ100LVEL11 | ECL/PECL 1:2 Differential Fanout Buffer |
| AZ100LVEL16 | ECL/PECL Differential Receiver |
| AZ100LVEL16VS | ECL/PECL Differential Receiver |
| AZ100LVEL16VT | ECL/PECL Oscillator Gain Stage & Buffer |
| AZ100LVEL16VV | Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer |
| AZ100LVEL58 | ECL/PECL 2:1 Multiplexer |
| AZ100LVE111 | ECL/PECL 1:9 Differential Clock Driver |
| AZ100LVE111 | ECL/PECL 1:9 Differential Clock Driver |
| AZ100LVE111E | ECL/PECL 1:9 Differential Clock Driver |
The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.