AD802 - Clock Recovery and Data Retiming Phase-Locked Loop

Analog Devices

Datasheet Details

Part number	AD802
Manufacturer	Analog Devices
File Size	253.42 KB
Description	Clock Recovery and Data Retiming Phase-Locked Loop
Datasheet	AD802 Datasheet

General Description

The AD800 and AD802 employ a second order phase-locked loop architecture to perform clock recovery and data retiming on Non-Return to Zero, NRZ, data.

This architecture is capable of supporting data rates between 20 Mbps and 160 Mbps.

The products described here have been defined to work with standard telecommunications bit rates.

Overview

Key Features

Standard Products 44.736 Mbps.
DS-3 51.84 Mbps.
STS-1 155.52 Mbps.
STS-3 or STM-1 Accepts NRZ Data, No Preamble Required Recovered Clock and Retimed Data Outputs Phase-Locked Loop Type Clock Recovery.
No Crystal Required Random Jitter: 20؇ Peak-to-Peak Pattern Jitter: Virtually Eliminated 10KH ECL Compatible Single Supply Operation:.
5.2 V or +5 V Wide Operating Temperature Range:.
40؇C to +85 ؇C Clock Recovery and Data Retiming Phase-Locked Loop AD80.

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