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AD73511 Datasheet Low-power CMOS Analog Front End

Manufacturer: Analog Devices

General Description

Y R A N L I M A I C L I E HN R P EC TA T DA ARITHMETIC UNITS ALU MAC SHIFTER ADSP-2100 BASE ARCHITECTURE REF PROGRAM MEMORY DATA DATA MEMORY DATA SERIAL PORTS SPORT 0 SPORT 1 TIMER FLASH MEMORY 64 KBYTES SERIAL PORT SPORT 2 ADC DAC ANALOG FRONT END SECTION The sampling rate of the AFE is programmable with four separate settings offering 64, 32, 16 and 8 kHz sampling rates (from a master clock of 16.384 MHz) while the serial port (SPORT2) allows easy expansion of the number of I/O channels by cascading extra AFEs external to the AD73511.

The AD73511’s DSP engine combines the ADSP-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities and on-chip program

Overview

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Key Features

  • AFE.