Datasheet Details
| Part number | AD7177-2 |
|---|---|
| Manufacturer | Analog Devices |
| File Size | 1.01 MB |
| Description | Sigma-Delta ADC |
| Download | AD7177-2 Download (PDF) |
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| Part number | AD7177-2 |
|---|---|
| Manufacturer | Analog Devices |
| File Size | 1.01 MB |
| Description | Sigma-Delta ADC |
| Download | AD7177-2 Download (PDF) |
|
|
|
32-bit data output Fast and flexible output rate: 5 SPS to 10 kSPS Channel scan data rate of 10 kSPS/channel (100 µs settling) Performance specifications 19.1 noise free bits at 10 kSPS 20.2 noise free bits at 2.5 kSPS 24.6 noise free bits at 5 SPS INL: ±1 ppm of FSR 85 dB filter rejection of 50 Hz and 60 Hz with 50 ms settling User configurable input channels 2 fully differential channels or 4 single-ended channels Crosspoint multiplexer On-chip 2.5 V reference (±2 ppm/°C drift) True rail-to-rail analog and reference input buffers The AD7177-2 is a 32-bit low noise, fast settling, multiplexed, 2-/4-channel (fully/pseudo differential) Σ-Δ analog-to-digital converter (ADC) for low bandwidth inputs.
It has a maximum channel scan rate of 10 kSPS (100 µs) for fully settled data.
The output data rates range from 5 SPS to 10 kSPS.
Data Sheet 32-Bit, 10 kSPS, Sigma-Delta ADC with 100 µs Settling and True Rail-to-Rail.
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