AS4C512M8D4A
Features
- JEDEC Standard pliant
- Fast clock rate: 1333MHz
- Power supplies:
- VDD & VDDQ = +1.2V ± 0.06V
- VPP = +2.5V -0.125V / +0.25V
- Operating temperature: -Industrial : TC = -40~95°C -mercial : TC = 0~95°C
- Supports JEDEC clock jitter specification
- Bidirectional differential data strobe, DQS &DQS#
- Differential Clock, CK & CK#
- 16 internal banks: 4 groups of 4 banks each
- Separated IO gating structures by Bank Group
- 8n-bit prefetch architecture
- Precharge & Active power down
- Auto Refresh and Self Refresh
- Low-power auto self refresh (LPASR)
- Self Refresh Abort
- Fine Granularity Refresh
- Dynamic ODT (RTT_PARK & RTT_Nom & RTT_WR)
- Write Leveling
- DQ Training via MPR
- Programmable preamble is supported both of 1t CK and 2t CK mode
- mand/Address (CA) Parity
- Data bus write cyclic redundancy check (CRC)
- Internal VREFDQ Training
- Read Preamble Training
- Control Gear Down Mode
- Per DRAM Addressability (PDA)
- Output Driver Impedance Control
- Dynamic on-die...
