Datasheet Details
| Part number | AS4C256M16D3LB-12BCN |
|---|---|
| Manufacturer | Alliance Semiconductor |
| File Size | 2.37 MB |
| Description | 4Gb DRAM |
| Datasheet |
 AS4C256M16D3LB-12BCN Datasheet
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General Description
Clock : CK and CK are differential clock inputs.
All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK.
Key Features
- - Double-data-rate architecture; two data transfers per clock cycle - The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture - Bi-directional differential data strobe (DQS and DQS) is transmitted/received with data for capturing data at the receiver - DQS is edge-aligned with data for READs; center-aligned with data for WRITEs - Differential clock inputs (CK and CK) - DLL aligns DQ and DQS transitions with CK transitions - Commands entered on each positive CK edge.