AS7C251MFT36A
Features
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- Organization: 1,048,576 words × 32 or 36 bits Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow-through operation Asynchronous output enable control Available in 100-pin TQFP package Individual byte write and global write
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- Multiple chip enables for easy expansion 2.5V core power supply Linear or interleaved burst control Snooze mode for reduced power-standby mon data inputs and data outputs
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Logic block diagram
LBO CLK ADV ADSC ADSP A[19:0] 20 CLK CE CLR Q0 Burst logic Q1
2 2
D Q CE Address register CLK D DQd Q Byte write registers CLK D DQ Q c Byte write registers CLK D DQb Q Byte write registers CLK D DQa Q Byte write registers CLK D Enable CE register CLK Q
1M × 32/36 Memory array
20 32/36 32/36
GWE BWE BWd
BWc
BWb
BWa CE0 CE1 CE2
OE Output registers CLK
Input registers CLK
Power down
D Enable Q delay register CLK 32/36 DQ[a:d]
Selection guide
Minimum cycle time Maximum...
