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UCN5895A - BiMOS II 8-BIT SERIAL INPUT / LATCHED SOURCE DRIVERS

Download the UCN5895A datasheet PDF. This datasheet also covers the UCN5895 variant, as both devices belong to the same bimos ii 8-bit serial input / latched source drivers family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • TA.
  • . . -20°C to +85°C Storage Temperature Range, TS.
  • . -55°C to +150°C s Low Output-Saturation Voltage s Source Outputs to 50 V s Output Current to -250 mA Caution: CMOS devices have input-static protection, but are susceptible to damage when exposed to extremely high static electrical s To 3.3 MHz Data-lnput Rate s Low-Power CMOS Logic & Latches charges. Always order by complete part number, e. g. , UCN5895A.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (UCN5895_Allegro.pdf) that lists specifications for multiple related part numbers.

Other Datasheets by Allegro MicroSystems

Part Number Description
UCN5895 BiMOS II 8-BIT SERIAL INPUT / LATCHED SOURCE DRIVERS
UCN5890 (UCN5891) BIMOS II 8-BIT SERIAL-INPUT / LATCHED SOURCE DRIVERS
UCN5800 (UCN5801) BiMOS II LATCHED DRIVERS
UCN5801 BiMOS II LATCHED DRIVERS
UCN5804 BiMOS II UNIPOLAR STEPPER-MOTOR TRANSLATOR/DRIVER
UCN5804B BiMOS II UNIPOLAR STEPPER-MOTOR TRANSLATOR/DRIVER
UCN5810AF LATCHED SOURCE DRIVERS
UCN5810F LATCHED SOURCE DRIVERS
UCN5810LWF LATCHED SOURCE DRIVERS
UCN5811 BiMOS II 12-BIT SERIAL-INPUT / LATCHED SOURCE DRIVERS

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Data Sheet 26182.14D 5895 BiMOS II 8-BIT SERIAL INPUT, LATCHED SOURCE DRIVERS The UCN5895A, UCN5895EP, and A5895SLW BiMOS II serial- UCN5895A input, latched source drivers are designed for applications emphasizing low output saturation voltages and currents to -250 mA per output. GROUND 1 SERIAL 16 DATA OUT These smart high-side octal, driver ICs merge an 8-bit CMOS shift register, associated CMOS latches, and CMOS control logic (strobe CLOCK SERIAL DATA IN 2 CLK 3 SHIFT REGISTER T STROBE 4 ST LATCHES VDD 15 OE 14 VBB 13 LOGIC SUPPLY OUTPUT ENABLE LOAD SUPPLY C OUT1 5 12 OUT 8 U OUT2 6 11 OUT7 D OUT3 7 10 OUT6 O OUT4 8 9 OUT5 PR ly Dwg.