The UT54ACS109 and the UT54ACTS109 are dual J-K positive triggered flip-flops.
A low level at the preset or clear inputs sets or resets the outputs regardless of the other input levels.
Key Features
radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack.
Full PDF Text Transcription for UT54ACS109 (Reference)
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UT54ACS109/UT54ACTS109
Radiation-Hardened Dual J-K Flip-Flops
FEATURES • • • • • • radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack
PINOUTS 16-Pin DIP Top View
CLR1 J K1 CLK1 PRE1 Q1 Q1 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD CLR2 J2 K2 CLK2 PRE2 Q2 Q2
DESCRIPTION The UT54ACS109 and the UT54ACTS109 are dual J-K positive triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the other input levels. When preset and clear are inactive (high), data at the J and K input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse.
UT54ACS109 Datasheet
