Datasheet4U Logo Datasheet4U.com

S4405 - Bicmos PLL Clock Generators

General Description

The S4405 BiCMOS clock generators allow the user to generate multiphase TTL clocks in the 10

80 MHz range with less than 400 ps of skew.

320 MHz phaselocked loop (PLL) to be implemented on-chip.

Key Features

  • Generates six clock outputs from 20 MHz to 80 MHz (HFOUT operates from 10 MHz to 40 MHz).
  • Allows PECL or TTL reference input.
  • Provides differential PECL output at up to 160 MHz.
  • 21 selectable phase/frequency relationships for the clock outputs.
  • Compensates for clock skew by allowing output delay adjustment down to 3.125 ns increments.
  • TTL outputs have less than 400 ps maximum skew.
  • Lock Detect output indicates loop status.

📥 Download Datasheet

Datasheet Details

Part number S4405
Manufacturer AMCC
File Size 134.06 KB
Description Bicmos PLL Clock Generators
Datasheet download datasheet S4405 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
S4402 Si-based Photodiodes Hamamatsu Photonic Systems
S4422B Switch color temperature controller SDsemi
S44233 Law Asynchronous Codec AMI Semiconductor
S446GA DOUBLER ASSEMBLY Sensitron

Other Datasheets by AMCC

Part Number Description

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
® DEVICE SPECIFICATION BiCMOS PECL CLOCK GENERATOR FEATURES • Generates six clock outputs from 20 MHz to 80 MHz (HFOUT operates from 10 MHz to 40 MHz) • Allows PECL or TTL reference input • Provides differential PECL output at up to 160 MHz • 21 selectable phase/frequency relationships for the clock outputs • Compensates for clock skew by allowing output delay adjustment down to 3.125 ns increments • TTL outputs have less than 400 ps maximum skew • Lock Detect output indicates loop status • Internal PLL with VCO operating at 160 to 320 MHz • Test Enable input allows VCO bypass for openloop operation • Maximum 1.0 ns of phase error (750 ps from part to part) • Proven 1.