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S19233
10 GbE/Fibre Channel/SONET/SDH/FEC Dual CDR
The system circuitry consists of a highspeed phase detector, clock dividers, and equalization circuitry. The device utilizes on-chip clock recovery/clock clean-up PLL components that allow the use of a slower external clock reference, 155.52 MHz (or equivalent FEC/10GbE/ 10 Gbps FC rates), in support of existing system clocking schemes. An equalizer is integrated in the receive front end of the TX side and it reshapes the data after transmission over a standard FR-4 material. This enables low bit error rate and transmission over longer distances. The device would allow users to meet the maximum dispersion penalty per ITU LR 2a, b, & c specifications with margin.
S19233 Datasheet
