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VDD8608A8A - DOUBLE DATA RATE SDRAM

Download the VDD8608A8A datasheet PDF. This datasheet also covers the VDD8608A8A-A variant, as both devices belong to the same double data rate sdram family and are provided as variant models within a single manufacturer datasheet.

Description

The ADD8616A8A are four-bank Double Data Rate(DDR) Synchronous DRAMs organized as 4,194,304 words x 16 bits x 4 banks, Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.

Features

  • 2.5V for VDDQ power supply.
  • SSTL_2 interface.
  • MRS Cycle with address key programs -CAS Latency (2, 2.5) -Burst Length (2,4 &8) -Burst Type (sequential & Interleave).
  • 4 banks operation.
  • Differential clock input (CK, /CK) operation.
  • Double data rate interface.
  • Auto & Self refresh.
  • 8192 refresh cycle.
  • DQM for masking.
  • Package:66-pins 400 mil TSOP-Type II Ordering Information. Part No. VDD8608A8A-75BA ADD8616A8A-75B Fr.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (VDD8608A8A-A-Data.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number VDD8608A8A
Manufacturer A-Data
File Size 205.93 KB
Description DOUBLE DATA RATE SDRAM
Datasheet download datasheet VDD8608A8A Datasheet

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Other Datasheets by A-Data

Part Number Description
VDD8616A8A DOUBLE DATA RATE SDRAM
VDD7616A4A DOUBLE DATA RATE SDRAM

Full PDF Text Transcription

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A-Data Revision History Revision 1 ( Dec. 2001 ) 1.Fister release. ADD8616A8A Revision 2 ( Apr. 2002 ) 1. Changed module current specification. 2. Add Performance range. 3. Changed AC Characteristics. 4. Changed typo size on module PCB in package dimensions. Rev 2 April, 2002 1 A-Data Double Data Rate SDRAM General Description The ADD8616A8A are four-bank Double Data Rate(DDR) Synchronous DRAMs organized as 4,194,304 words x 16 bits x 4 banks, Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Data outputs occur at both rising edges of CK and /CK.
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