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VDS6632A4A - Synchronous DRAM

Download the VDS6632A4A datasheet PDF. This datasheet also covers the VDS6632A4A_A variant, as both devices belong to the same synchronous dram family and are provided as variant models within a single manufacturer datasheet.

Description

The VDS6632A4A are four-bank Synchronous DRAMs organized as 524,288 words x 32 bits x 4 banks, Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.

Features

  • JEDEC standard LVTTL 3.3V power supply.
  • MRS Cycle with address key programs -CAS Latency (2 & 3) -Burst Length (1,2,3,8,& full page) -Burst Type (sequential & Interleave).
  • 4 banks operation.
  • All inputs are sampled at the positive edge of the system clock.
  • Burst Read single write operation.
  • Auto & Self refresh.
  • 4096 refresh cycle.
  • DQM for masking.
  • Package:86-pins 400 mil TSOP-Type II Ordering Information. Part No. Frequen.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (VDS6632A4A_A-DataTechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number VDS6632A4A
Manufacturer A-Data Technology
File Size 228.13 KB
Description Synchronous DRAM
Datasheet download datasheet VDS6632A4A Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
V-Data Synchronous DRAM VDS6632A4A 512K x 32 Bit x 4 Banks General Description The VDS6632A4A are four-bank Synchronous DRAMs organized as 524,288 words x 32 bits x 4 banks, Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features •JEDEC standard LVTTL 3.
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