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74HCT164 - shift register

Download the 74HCT164 datasheet PDF. This datasheet also covers the 74HC164 variant, as both devices belong to the same shift register family and are provided as variant models within a single manufacturer datasheet.

Description

The 74HC164; 74HCT164 is an 8-bit serial-in/parallel-out shift register.

Features

  • Wide supply voltage range from 2.0 to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Input levels:.
  • For 74HC164: CMOS level.
  • For 74HCT164: TTL level.
  • Gated serial data inputs.
  • Asynchronous master reset.
  • Complies with JEDEC standards.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A (2.0 V to 6.0 V).
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • ESD protection:.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC164-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74HCT164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS Diodes
74HCT164 8-bit serial-in / parallel-out shift register NXP
74HCT160 Presettable synchronous BCD decade counter Philips
74HCT161 Presettable synchronous 4-bit binary counter Philips
74HCT162 Presettable synchronous BCD decade counter Philips

Other Datasheets by Nexperia

Part Number Description
74HCT164-Q100 shift register
74HCT164D shift register
74HCT163 Presettable synchronous 4-bit binary counter
74HCT163-Q100 Presettable synchronous 4-bit binary counter
74HCT163D Presettable synchronous 4-bit binary counter

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC164; 74HCT164 8-bit serial-in, parallel-out shift register Rev. 11 — 28 May 2024 Product data sheet 1. General description The 74HC164; 74HCT164 is an 8-bit serial-in/parallel-out shift register. The device features two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7). Data is entered serially through DSA or DSB and either input can be used as an active HIGH enable for data entry through the other input. Data is shifted on the LOW-to-HIGH transitions of the clock (CP) input. A LOW on the master reset input (MR) clears the register and forces all outputs LOW, independently of other inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2.
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