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74HCT112 - Dual JK flip-flop

Download the 74HCT112 datasheet PDF. This datasheet also covers the 74HC112 variant, as both devices belong to the same dual jk flip-flop family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop.

Key Features

  • Input levels:.
  • For 74HC112: CMOS level.
  • For 74HCT112: TTL level.
  • Asynchronous set and reset.
  • Specified in compliance with JEDEC standard no. 7A.
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74HC112D -40 °C to +125 °C 74HCT11.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC112-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74HCT112 Dual JK flip-flop Philips
74HCT11 Triple 3-input AND gate Philips
74HCT11 Triple 3-input AND gate NXP
74HCT10 Triple 3-input NAND gate Philips
74HCT107 Dual JK flip-flop Philips

Other Datasheets by Nexperia

Part Number Description
74HCT112D Dual JK flip-flop
74HCT11 Triple 3-input AND gate
74HCT11-Q100 Triple 3-input AND gate
74HCT11D Triple 3-input AND gate
74HCT11DB Triple 3-input AND gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC112; 74HCT112 Dual JK flip-flop with set and reset; negative-edge trigger Rev. 4 — 11 January 2021 Product data sheet 1. General description The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.