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74HC4060PW - 14-stage binary ripple counter

Download the 74HC4060PW datasheet PDF. This datasheet also covers the 74HC4060 variant, as both devices belong to the same 14-stage binary ripple counter family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74HC4060; 74HCT4060 is a 14-stage ripple-carry counter/divider and oscillator with three oscillator terminals (RS, RTC and CTC), ten buffered parallel outputs (Q3 to Q9 and Q11 to Q13) and an overriding asynchronous master reset (MR).

Key Features

  • Wide supply voltage range from 2.0 V to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • All active components on chip.
  • RC or crystal oscillator configuration.
  • Input levels:.
  • For 74HC4060: CMOS level.
  • For 74HCT4060: TTL level.
  • Complies with JEDEC standards:.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A (2.0 V to 6.0 V).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC4060-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74HC4060PW
Manufacturer Nexperia
File Size 317.12 KB
Description 14-stage binary ripple counter
Datasheet download datasheet 74HC4060PW Datasheet

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Other Datasheets by Nexperia

Part Number Description
74HC4060 14-stage binary ripple counter
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC4060; 74HCT4060 14-stage binary ripple counter with oscillator Rev. 7 — 27 March 2024 Product data sheet 1. General description The 74HC4060; 74HCT4060 is a 14-stage ripple-carry counter/divider and oscillator with three oscillator terminals (RS, RTC and CTC), ten buffered parallel outputs (Q3 to Q9 and Q11 to Q13) and an overriding asynchronous master reset (MR). The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may be replaced by an external clock signal at input RS. In this case, keep the oscillator pins (RTC and CTC) floating. The counter advances on the HIGH-to-LOW transition of RS. A HIGH level on MR clears all counter stages and forces all outputs LOW, independent of the other input conditions. Inputs include clamp diodes.