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74HC237D - 3-to-8 line decoder/demultiplexer

Download the 74HC237D datasheet PDF. This datasheet also covers the 74HC237 variant, as both devices belong to the same 3-to-8 line decoder/demultiplexer family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An).

The 74HC237 essentially combines the 3-to-8 decoder function with a 3-bit storage latch.

When the latch is enabled (LE = LOW), the 74HC237 acts as a 3-to-8 active LOW decoder.

Key Features

  • Combines 3-to-8 decoder with 3-bit latch.
  • Multiple input enable for easy expansion or independent controls.
  • Active HIGH mutually exclusive outputs.
  • Wide supply voltage range from 2.0 V to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Complies with JEDEC standards:.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A (2.0 V to 6.0 V).
  • ESD prot.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC237-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74HC237D
Manufacturer Nexperia
File Size 258.72 KB
Description 3-to-8 line decoder/demultiplexer
Datasheet download datasheet 74HC237D Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC237 3-to-8 line decoder, demultiplexer with address latches Rev. 9 — 11 January 2024 Product data sheet 1. General description The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC237 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the 74HC237 acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE remains HIGH. The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH.