74AHC74-Q100 Datasheet (nexperia) - Dual D-type flip-flop

74AHC74-Q100, Dual D-type flip-flop

The 74AHC74-Q100; 74AHCT74-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL).

It is specified in compliance with JEDEC standard No.

7-A.

The 74AHC74-Q100; 74AHCT74-Q100 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D

74AHC74-Q100 Features

* Automotive product qualification in accordance with AEC-Q100 (Grade 1)

* Specified from -40 °C to +85 °C and from -40 °C to +125 °C

* Balanced propagation delays

* All inputs have Schmitt-trigger actions

* Inputs accept voltages higher than VCC

* Inp