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SN74165 - Parallel-Load 8-Bit Shift Registers

Description

The ’165 and ’LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked.

Parallel-in access to each stage is made available by eight individual, direct data inputs that are enabled by a low level at the shift/load (SH/LD) input.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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The SN54165 and SN74165 devices are obsolete and are no longer supplied. SN54165, SN54LS165A, SN74165, SN74LS165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002 D Complementary Outputs D Direct Overriding Load (Data) Inputs D Gated Clock Inputs D Parallel-to-Serial Data Conversion TYPE ’165 ’LS165A TYPICAL MAXIMUM CLOCK FREQUENCY 26 MHz 35 MHz TYPICAL POWER DISSIPATION 210 mW 90 mW description The ’165 and ’LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual, direct data inputs that are enabled by a low level at the shift/load (SH/LD) input.
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