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SN65LVDS96 LVDS SERDES RECEIVER

SN65LVDS96 Description

SN65LVDS96 www.ti.com LVDS SERDES RECEIVER SLLS296H * MAY 1998 * REVISED JULY 2006 .
The SN65LVDS96 LVDS serdes (serializer/deserializer) receiver contains three serial-in 7-bit parallel-out shift registers, a 7× clock synthesizer, and.

SN65LVDS96 Features

* 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput
* Suited for Point-to-Point Subsystem Communication With Very Low EMI
* 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out
* Operates Fr

SN65LVDS96 Applications

* of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not neces

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LVDS SERDES RECEIVER Texas Instruments
Texas Instruments SN65LVDS96-like datasheet