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DS90CF366 - 3.3-V LVDS Receiver

Description

The DS90CF386 receiver converts four LVDS (Low Voltage Differential Signaling) data streams back into parallel 28 bits of LVCMOS data.

Also available is the DS90CF366 receiver that converts three LVDS data streams back into parallel 21 bits of LVCMOS data.

Features

  • 1 20-MHz to 85-MHz Shift Clock Support.
  • Rx Power Consumption 700 V (EIAJ).
  • Supports VGA, SVGA, XGA, and Single Pixel SXGA.
  • PLL Requires No External Components.
  • Compatible With TIA/EIA-644 LVDS Standard.
  • Low Profile 56-Pin or 48-Pin TSSOP Package.
  • DS90CF386 Also Available in a 64-Pin, 0.8-mm, Fine Pitch Ball Grid Ar.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Product Folder Sample & Buy Technical Documents Tools & Software Support & Community DS90CF366, DS90CF386 SNLS055J – NOVEMBER 1999 – REVISED MAY 2016 DS90CF3x6 3.3-V LVDS Receiver 24-Bit Or 18-Bit Flat Panel Display (FPD) Link, 85 MHz 1 Features •1 20-MHz to 85-MHz Shift Clock Support • Rx Power Consumption <142 mW (Typical) at 85-MHz Grayscale • Rx Power-Down Mode <1.44 mW (Maximum) • ESD Rating >7 kV (HBM), >700 V (EIAJ) • Supports VGA, SVGA, XGA, and Single Pixel SXGA • PLL Requires No External Components • Compatible With TIA/EIA-644 LVDS Standard • Low Profile 56-Pin or 48-Pin TSSOP Package • DS90CF386 Also Available in a 64-Pin, 0.
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