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CDCLVP111 Low-Voltage 1:10 LVPECL

CDCLVP111 Description

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CDCLVP111 SCAS859F * JANUARY 2009 * REVISED .
The CDCLVP111 clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) ou.

CDCLVP111 Features

* 1 Distributes One Differential Clock Input Pair LVPECL to 10 Differential LVPECL
* Fully Compatible With LVECL and LVPECL
* Supports a Wide Supply Voltage Range from 2.375 V to 3.8 V
* Selectable Clock Input Through CLK_SEL
* Low-Output Skew (Typical 15 ps) f

CDCLVP111 Applications

* Additive Jitter Less Than 1 ps
* Propagation Delay Less Than 350 ps
* Open Input Default State
* LVDS, CML, SSTL Input Compatible
* VBB Reference Voltage Output for Single-Ended Clocking
* Available in a 32-Pin LQFP and QFN Package
* Frequenc

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