CDC857-2 Datasheet (Texas Instruments) - 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS

CDC857-2, 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS

VCC 11 VCC 12 CLK 13 38 VCC 37 G 36 FBIN The CDC857-2 and CDC857-3 are high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver.

They use a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

The CDC857-3 operates at

CDC857-2, CDC857-3 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS SCAS627A SEPTEMBER 1999 DECEMBER 1999 D Phase-Lock Loop Clock Distribution for Double Data Rate Synchronous DRAM DGG PACKAGE (TOP VIEW) Applications D Distributes One Differential Clock Input to Ten Differential Outputs D External Feedback Pins (FBIN, FBIN) Are Used to Synchronize the Outputs to the Clock Input D Operates at VCC = 2.5 V and AVCC = 3.3 V D Packaged in Plastic 48-Pin (DGG) Thin Shrink Small-Outlin