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CDC509 - 3.3-V Phase-Lock-Loop Clock Driver

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CDC509 Product details

Description

NOT RECOMMENDED FOR NEW DESIGNS PW PACKAGE (TOP VIEW) AGND 1 VCC 2 1Y0 3 1Y1 4 1Y2 5 GND 6 GND 7 1Y3 8 1Y4 9 VCC 10 1G 11 FBOUT 12 24 CLK 23 AVCC 22 VCC 21 2Y0 20 2Y1 19 GND 18 GND 17 2Y2 16 2Y3 15 VCC 14 2G 13 FBIN The CDC509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver.It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.It is specifically designed for use with synchronous DRAMs.The

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