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CDC3S04 - Quad Sine-Wave Clock Buffer

Description

The CDC3S04 is a four-channel low-power low-jitter sine-wave clock buffer.

It can be used to buffer a single master clock to multiple peripherals.

CLK4) are designed for minimal channel-to-channel skew and ultralow additive output jitter.

Features

  • 1.
  • 1:4 Low-Jitter Clock Buffer.
  • Single-Ended Sine-Wave Clock Input and Outputs.
  • Ultralow Phase Noise and Standby Current.
  • Individual Clock Request Inputs for Each Output.
  • On-Chip Low-Dropout Output (LDO) for Low- Noise TCXO Supply.
  • Serial I2C Interface (Compatible With High- Speed Mode, 3.4 Mbit/s).
  • 1.8-V Device Power Supply.
  • Wide Temperature Range,.
  • 40°C to 85°C.
  • ESD Protection: 2 KV HBM, 750 V CDM, and 100.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.ti.com CDC3S04 SCAS883C – OCTOBER 2009 – REVISED AUGUST 2012 Quad Sine-Wave Clock Buffer With LDO Check for Samples: CDC3S04 FEATURES 1 • 1:4 Low-Jitter Clock Buffer • Single-Ended Sine-Wave Clock Input and Outputs • Ultralow Phase Noise and Standby Current • Individual Clock Request Inputs for Each Output • On-Chip Low-Dropout Output (LDO) for Low- Noise TCXO Supply • Serial I2C Interface (Compatible With High- Speed Mode, 3.4 Mbit/s) • 1.8-V Device Power Supply • Wide Temperature Range, –40°C to 85°C • ESD Protection: 2 KV HBM, 750 V CDM, and 100 V MM • Small 20-Pin Chip-Scale Package: 0.4-mm Pitch WCSP (1.
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