Description
DW OR NT PACKAGE (TOP VIEW)
1CLK 1Q1 1Q2 1Q3 1Q4 GND GND GND GND 2Q1 2Q2 2Q3 2Q4
2CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 1OE 27 1CLR 26 1D1 25 1D2 24 1D3 23 1D4 22 VCC 21 VCC 20 2D1 19 2D2 18 2D3 17 2D4 16 2CLR 15 2OE
This dual 4-bit D-type edge-triggered flip-flop
Features
- 3-state outputs designed specifically for bus driving. This makes these devices particularly suitable for implementing buffer registers, I/O ports, and working registers. The flip-flops enter data on the low-to-high transition of the clock. The 74AC11874 has clear (1CLR and 2CLR) inputs and noninverting outputs. Taking CLR low causes the four Q outputs to go low independently of the clock. The 74AC11874 is characterized for operation from.
- 40°C to 85°C.
74AC11874-etcTI.pdf
