74AC11112 Datasheet - Texas Instruments

74AC11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

1CLK 1CLR NC V CC 2CLR These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs .

54AC11112, 74AC11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS073A JUNE 1989 REVISED APRIL 1993 Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise EPIC ™ (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C ESD Protection Exceeds 2000 V, MIL STD-883C Method 3015 Package Options I.

74AC11112-etcTI.pdf