A3V28S40JTP - 128M Single Data Rate Synchronous DRAM

Zentel

Datasheet Details

Part number	A3V28S40JTP
Manufacturer	Zentel
File Size	945.93 KB
Description	128M Single Data Rate Synchronous DRAM
Datasheet	A3V28S40JTP-Zentel.pdf

A3V28S40JTP is organized as 4-bank x 2,097,154-word x 16-bit Synchronous DRAM with LVTTL interface.

- Single 3.3V ±0.3V power supply - Maximum clock frequency : - 60:166MHz/-70:143MHz/-75:133MHz - Fully synchronous operation referenced to clock rising edge - 4-bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/FP (programmable) - Burst type- Sequential and interleave burst (programmable) - Byte Control- LDQM and UDQM (A3V28S40JTP) - Random column access - Auto precharge / All bank precharge controlled by A10 - Su.

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Published: Sep 1, 2015 |