PDSP16318MC Datasheet (Zarlink Semiconductor)

PDSP16318MC, Complex Accumulator

The PDSP16318 is a Dual 20-bit Adder/Subtractor configured to supprt Complex Arithmetic.

The device may be used with each of the adders allocated to real or imaginary data (e.g.

Complex Conjugation), the entire device allocated to Real or Imaginary Data (e.g.

Radix 2 Butterflys) or each of the adder

www.DataSheet4U.com PDSP16318 MC PDSP16318 MC Complex Accumulator DS3761 ISSUE 2.1 November 1998 The PDSP16318 contains two independent 20-bit Adder/ Subtractors combined with accumulator registers and shift structures.

The four port architecture permits full 10MHz throughout in FFT and filter applications.

Two PDSP16318s combined with a single PDSP16112A Complex Multiplier provide a complete arithmetic solution for a Radix 2 DIT FFT Butterfly.

A new complex Butterfly result can be generate

PDSP16318MC Features

* s s s s s s s s s s Full 10MHz Throughout in FFT Applications Four Independent 16-bit I/O Ports 20-bit Addition or Accumulation Fully Compatible with PDSP16112 Complex Multiplier On Chip Shift Structures for Result Scaling Overflow Detection Independent Three-State Outputs and Clock Enables for 2