CLA90000 - High Density CMOS Gate Arrays

Zarlink Semiconductor

Datasheet Details

Part number	CLA90000
Manufacturer	Zarlink Semiconductor
File Size	458.15 KB
Description	High Density CMOS Gate Arrays
Datasheet	CLA90000_ZarlinkSemiconductor.pdf

I Low power, 0.5µW/MHz/gate at 3V supply (NAND 2 loads) I High density of 5,425 available gates/mm2 I 3V and 5V I/O capability on the same device I 150ps gate delay for 2-input NAND with two loads (5V) I Accurate delay modelling for gates and tracks with sign off quality CAE design libraries for QuickSim II and Verilog-XL I CAD libraries optimized for synthesis I Up to 512K available gates and 352 pads with ﬁxed arrays I Up to 1.1M available gates and 520 pads with optimized arrays I Double or t.

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Published: Apr 24, 2006 |