UD61466 Datasheet (ZMD)

UD61466, DRAM

meanwhile LOW leads to a Write cycle.

Addressing The UD61466 is a dynamic random Both CAS-controlled and W-controlaccess memory organized 65536 led Write cycles are possible with words by 4 bits.

activated RAS signal.

Pin Configuration Pin Description (OE) G DQ0 DQ1 1 2 3 4 5 6 7 8 9 18 17 16

UD61466 Features

* UD61466 64K x 4 DRAM SCM facilitates faster data operation with predefined row address. Via 8 address inputs the 16 address bits are transmitted into the internal address memories in a time-multiplex operation. The falling RASedge takes over the row address. After the row address hold time the colu