XCR3512XL Datasheet (Xilinx) - 512 Macrocell CPLD

XCR3512XL, 512 Macrocell CPLD

The XCR3512XL is a 3.3V, 512 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions.

A total of 32 function blocks provide 12,800 usable gates.

Pin-to-pin propagation delays are 7.5 ns with a maximum system frequency of 127 MHz.

TotalCMOS™ Design T

XCR3512XL Features

* Lowest power 512 macrocell CPLD 7.5 ns pin-to-pin logic delays System frequencies up to 127 MHz 512 macrocells with 12,800 usable gates Available in small footprint packages - 208-pin PQFP (180 user I/O) - 256-ball FBGA (212 user I/O) - 324-ball FBGA