XCR3512XL - 512 Macrocell CPLD

Xilinx

Datasheet Details

The XCR3512XL is a 3.3V, 512 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions.

Lowest power 512 macrocell CPLD 7.5 ns pin-to-pin logic delays System frequencies up to 127 MHz 512 macrocells with 12,800 usable gates Available in small footprint packages - 208-pin PQFP (180 user I/O) - 256-ball FBGA (212 user I/O) - 324-ball FBGA (260 user I/O) Optimized for 3.3V systems - Ultra low power operation - 5V tolerant I/O pins with 3.3V core supply - Advanced 0.35 micron five layer metal EEPROM process - FZP™ CMOS design technology.

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Published: Jan 9, 2010 |