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W3E32M72S-XBX - 32Mx72 DDR SDRAM

General Description

The 256MByte (2Gb) DDR SDRAM is a high-speed CMOS, dynamic random-access, memory using 5 chips containing 536,870,912 bits.

Each chip is internally configured as a quad-bank DRAM.

The 256MB DDR SDRAM uses a double data rate ar chi tec ture to achieve high-speed operation.

Key Features

  • Data rate = 200, 250, 266, 333Mbs Package:.
  • 219 Plastic Ball Grid Array (PBGA), 32 x 25mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK#) Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ received with data, i. e. , source-synchronous data capture (one per byte) DQS edge-aligned w.

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Datasheet Details

Part number W3E32M72S-XBX
Manufacturer White Electronic
File Size 695.33 KB
Description 32Mx72 DDR SDRAM
Datasheet download datasheet W3E32M72S-XBX Datasheet

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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White Electronic Designs 32Mx72 DDR SDRAM FEATURES Data rate = 200, 250, 266, 333Mbs Package: • 219 Plastic Ball Grid Array (PBGA), 32 x 25mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK#) Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (one per byte) DQS edge-aligned with data for READs; centeraligned with data for WRITEs www.DataSheet4U.com W3E32M72S-XBX BENEFITS 40% SPACE SAVINGS vs.