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UR5596 - DDR TERMINATION REGULATOR

The UR5596 by UTC is a DDR TERMINATION REGULATOR. Below is the official datasheet preview.

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Official preview page of the UR5596 DDR TERMINATION REGULATOR datasheet (UTC).

Datasheet Details

Part number UR5596
Manufacturer UTC
File Size 351.47 KB
Description DDR TERMINATION REGULATOR
Datasheet download datasheet UR5596_UTC.pdf
Additional preview pages of the UR5596 datasheet.

UR5596 Product details

Description

The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM.

Features

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